Electrical engineering

Digital logic

Boolean algebra, gates, flip-flops, and timing.

Basics

Boolean algebra

True/false become 1/0, combined with AND, OR, and NOT. De Morgan swaps AND and OR with bubbles. A truth table lists every input; Karnaugh maps or tools shrink the expression. Hardware uses voltage bands for 1 and 0. Mid-band voltages are forbidden. Do not mix positive and negative logic on one drawing.

Gates

NAND and NOR are each functionally complete. XOR is the sum bit without carry. In CMOS, NAND often uses fewer transistors than AND, so synthesis lowers to NAND. Heavy fan-out stretches delay and breaks timing. Read t_pd on the datasheet.

Flip-flops and state

Combinational logic cannot remember. Latches and edge-triggered flip-flops hold a bit. The D flip-flop is the register primitive. A machine that steps on a clock is a finite-state machine. Violating setup or hold time risks metastability. Asynchronous inputs need synchronisers when crossing into a clock domain.

Timing

The fastest clock is set by the longest combinational path plus flip-flop delay. Races and glitches appear when inputs change together. Debounce filters a mechanical switch. Resets are often asynchronous assert, synchronous deassert. A simulated waveform is not silicon, but it is the first hunt for violations.

Formulas

De Morgan

¬(A ∧ B) = ¬A ∨ ¬B, ¬(A ∨ B) = ¬A ∧ ¬B

Moving bubbles turns NAND into NOR and back.

XOR

A ⊕ B = (A ∨ B) ∧ ¬(A ∧ B)

1 iff they differ. Sum bit of a half adder.

Max clock (sketch)

T_clk ≥ t_cq + t_logic + t_su

Clock-to-Q, combinational, setup. Skew and jitter eat slack.

Symbols

t_cq clock-to-Q
t_su setup time

Key table

NAND complete	NOT is NAND with tied inputs; AND is NAND then NOT
Edge	rising (posedge) or falling. datasheet mark ▷
Pull-up	open collector/drain needs a resistor to make a 1